`timescale 1ns/1ps
module Rom_tb;
reg clk;
reg rst_n;
reg [4:0] num;
reg [3:0] row;
wire [3:0] col;
wire [7:0] q;
initial begin
clk <= 1′b1;
rst_n <= 1’b0;
#20 rst_n <= 1’b1;
#100 num <= 5′h1;
#500 num <= 5′h1F;
#10000 num <= 5′h2;
#500 num <= 5’h1F;
#10000 num <= 5’h3;
#500 num <= 5’h1F;
#10000 num <= 5’h4;
#500 num <= 5’h1F;
end
Rom RomInst(
.clk (clk),
.rst_n (rst_n),
.row (row),
.col (col),
.q (q)
);
always @ (*)
begin
case (num)
5’h0: row <= {1’b1, 1’b1, 1’b1, col[0]};
5’h1: row <= {1’b1, 1’b1, 1’b1, col[1]};
5’h2: row <= {1’b1, 1’b1, 1’b1, col[2]};
5’h3: row <= {1’b1, 1’b1, 1’b1, col[3]};
5’h4: row <= {1’b1, 1’b1, col[0], 1’b1};
5’h5: row <= {1’b1, 1’b1, col[1], 1’b1};
5’h6: row <= {1’b1, 1’b1, col[2], 1’b1};
5’h7: row <= {1’b1, 1’b1, col[3], 1’b1};
5’h8: row <= {1’b1, col[0], 1’b1, 1’b1};
5’h9: row <= {1’b1, col[1], 1’b1, 1’b1};
5’hA: row <= {1’b1, col[2], 1’b1, 1’b1};
5’hB: row <= {1’b1, col[3], 1’b1, 1’b1};
5’hC: row <= {col[0], 1’b1, 1’b1, 1’b1};
5’hD: row <= {col[1], 1’b1, 1’b1, 1’b1};
5’hE: row <= {col[2], 1’b1, 1’b1, 1’b1};
5’hF: row <= {col[2], 1’b1, 1’b1, 1’b1};
default: row <= {1’b1, 1’b1, 1’b1, 1’b1};
endcase
end
defparam RomInst.KeyScanInst.T10ms = 5;
原文地址:https://blog.csdn.net/durongze/article/details/134583292
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