`timescale 1ns/1ps
module Rom_tb;
reg clk;
reg rst_n;
reg [4:0] num;
reg [3:0] row;
wire [3:0] col;
wire [7:0] q;
initial begin
clk <= 1′b1;
rst_n <= 1’b0;
#20 rst_n <= 1’b1;
#100 num <= 5′h1;
#500 num <= 5′h1F;
#10000 num <= 5′h2;
#500 num <= 5’h1F;
#10000 num <= 5’h3;
#500 num <= 5’h1F;
#10000 num <= 5’h4;
#500 num <= 5’h1F;
end
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