EEE201Digital Integrated Circuits

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1. 1.1 SCMOS Design RulesThis document defines the official MOSIS scalable CMOS (SCMOS) layout rules. It supersedes allprevious revisions.In the SCMOS rules, circuit geometries are specified in the Mead and Conway’s lambda basedmethodology [1]. The unit of measurement, lambda, can easily be scaled to different fabricationprocesses as semiconductor technology advances.Each design has atechnology–codeassociated with the layout file. At the moment, threetechnology-codes are used to specify the basic CMOS process. Each technology-code may have one ormore associatedoptionsadded for the purpose of specifying either (a) special features for the targetprocess or (b) the presence of novel devices in the design. At the time of this revision, MOSIS isoffering six CMOS processes from three different foundries with feature sizes from 2.0 micron to 0.5micron.2 Standard SCMOSThe standard CMOS technology accessed by MOSIS is a single polysilicon, double metal, bulk CMOSprocess with enhancement-mode n-MOSFET and p-MOSFET devices [3].2.1 Well TypeThree technology-codes are used to indicate the well type (substrate) used for fabrication (as shown inTable 1).

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   Technology-CodeDescriptionSCNScalable CMOS N-wellSCPScalable CMOS P-wellSCEScalable CMOS Either-wellTable 1: SCMOS well typesThe SCN and SCP technology-codes are used when submitting a design for fabrication in a process ofthe specified well. For convenience, in either case, the layout file may contain the ’other’ well, but it willalways be ignored.Designs specifying the SCE technology-code may be fabricated in any CMOS process, N-well or P-well(either) and must include both wells (and correspondingly, well/substrate contacts for proper bias). Forany given fabrication process the ’other’ well be ignored during mask generation. If twin-tub processesare offered in the future, both wells will be used.Note:Currently MOSIS only offers n-well processes.2.2 SCMOS OptionsSCMOS options are used to designate projects that use additional layers beyond the standardsingle-poly, double metal CMOS. Each option is called out with a designator that is appended to thebasic technology-code. Please note that not all possible combinations are available. The current list isshown in Table 2.DesignationLong FormDescriptionEElectrodeAdds a second polysilicon layer (electrode) that can serveeither as the upper electrode of a poly capacitor or as a gate fortransistors.AAnalogAdds electrode (as in E option), plus layers for vertical NPNtransistor pbase and buried CCDs.3MTriple MetalAdds second via (via2) and third metal (metal3) layers.4MQuad MetalAdds 3M plus third via (via3) and fourth metal (metal4) layers.LCLinear CapacitorAdds a cap_well layer for linear capacitors._MEMSMicro MachiningAdds mems_open and mems_etch_stop for CMOS-compatibleMEMS devices._SUBMSub MicronUses revised layout rules for better fit to submicron processes(see section 2.4).Table 2: SCMOS technology optionsIn addition to the options in Table 2, two undeclared options exist. The first is for high voltage

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   MOSFET. The second is for a tight metal rule for metal interconnect. For options available to specificprocesses, see Tables 3a and 3b.FoundryProcessLambdaOptionsOrbit2.0um N-well1.0umSCNA, SCNE, SCN,SCNA_MEMSAMIABN (1.2um N-well)0.6umSCNA(1), SCNE, SCN, HighVoltageHPCMOS34 / AMOSI (1.2um N-well)0.6umSCNLC, SCN, Tight MetalHPCMOS26G (0.8um N-well)0.5umSCN3M, SCN, Tight MetalAMICWL (0.8um N-well)0.5umSCNPC, Tight MetalHPGMOS14TB/AMOS14TB (0.5um N-well)0.35umSCN3M, SCN, SCN3MLC,SCNLC,Tight MetalHPGMOS10QA (0.35um N-well)0.25umSCN4N, Tight MetalTable 3a: MOSIS SCMOS-compatible mappingsFoundryProcessLambdaOptionsHPCMOS26G (0.8um N-well)0.4umSCN3M_SUBM, SCN_SUBMHPGMOS14TB/AMOS14TB (0.5umN-well)0.3umSCN3M_SUBM, SCN_SUBM,SCN3MLC_SUBM, SCNLC_SUBMHPGMOS10QA (0.35um N-well)0.2umSCN4M_SUBMTable 3b: MOSIS SCMOS_SUBM-compatible mappings2.3 SCMOS-compatible processesMOSIS currently offers the fabrication processes shown above in Tables 3a and 3b. For each process thelist of appropriate SCMOS technology-codes is shown. Note that whenever SCNxx appears, SCExx isalso appropriate.2.4 SCMOS_SUBM – Sub Micron RulesThe SCMOS layout rules were historically developed for 1.0 to 3.0 micron processes. To take fulladvantage of advanced submicron processes, the SCMOS rules were revised to create SCMOS_SUBM.By increasing the lambda size for some rules (those that didn’t shrink as fast in practice as did theoverall scheme of things), the submicron rules allow for use of a smaller value of lambda, and better fitto these small feature size processes. Table 4 lists the differences between SCMOS, SCMOS tight metaland SCMOS sub-micron.

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   DescriptionRuleSCMOSSCMOS tight metalSCMOS sub-micronWell width1.1101012Well space (different potential)1.29918Well overlap (space) to transistor2.3556Poly space3.2223Contact space5.3, 6.3223Metal1 space7.2323Via on flat8.522unrestrictedMetal2 space9.2433Metal3 width15.1665Metal3 space15.2443Table 4: SCMOS, SCMOS tight metal, SCMOS Sub-micron differences3 CIF and GDS layer specificationA user design submitted to MOSIS using the SCMOS rules can be in either Calma GDSII format [2] orCaltech Intermediate Form (CIF version 2.0) [1]. The two are completely interchangable. Note that allsubmitted cif and gds files have already been scaled before submission, and are always in absolutemetric units — never in lambda units.GDSII is a binary format, while CIF is a plain ASCII text. For detailed syntax and semanticspecifications of GDS and CIF, refer to [2] and [1] respectively.In GDS format, a design layer is specified as a number between 0 and 255 (formerly 63). MOSISSCMOS now reserves layer numbers 21 through 62, inclusive, for drawn layout. Layers 0 through 20plus layers 63 and above can be used by designers for their own purposes and will be ignored byMOSIS.In this revision, nine new layers were added as shown below:P-high-voltageis used to indicate high-voltage p-type areas.N-high-voltageis used to indicate high-voltage n-type areas.MEMS-openis used to indicate substrate pit opening area for MEMS devices.MEMS-etch-stopis used to indicate substrate p+ etch-stop area for MEMS devices.Contactreplaces the previously separate poly-contact, active-contact and electrode-contact layers.

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   Padsis used to indicate bonding pad locations.Explicit field implantdenotes the field implant reversal layer.Poly-capsupports the AMI-style linear capacitor called SCNPC. It has the regular (two-metal) SCNlayers, plus the new layer POLY_CAP1.Silicide blockis used for blocking the siliciding of poly and/or active.Users should be aware that there is only one contact mask layer, although several separate layers weredefined and are retained for backward compatibility. A complete list of SCMOS layers is shown inTable 5.SCMOS layerCIF nameGDS2 numberSCMOS layerCIF nameGDS2 numberP-high-voltageCVP21PolyCPG46N-high-voltageCVN22ContactCCG25MEMS-openCOP23Metal1CMF49MEMS-etch-stopCPS24ViaCVA50PadXP26Metal2CMS51Explicit field implantCFI27GlassCOG52Poly-capCPC28ElectrodeCEL56Silicide blockCSB29Buried-CCDCCD57P-wellCWP41P-baseCBA58N-wellCWN42Cap-wellCWC59ActiveCAA43Via2CVS61P-plus–selectCSP44Metal3CMT62N-plus-selectCSN45Via3CVT30—Metal4CMQ31Table 5: SCMOS layer mapReferences[1] C. Mead and L. Conway,Introduction to VLSI Systems, Addison-Wesley, 1980[2] Cadence Design Systems, Inc./Calma.GDSII Stream Format Manual, Feb. 1987, Release 6.0,Documentation No. B97E060

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   [3] N. H. E. Weste and K. Eshraghian,Principles of CMOS VLSI Design: A System Perspective,Addison-Wesley, 2nd edition, 1993SCMOS Layout Rules – WellRuleDescriptionLambda1.1Minimum width10[SUBM 12]1.2Minimum spacing between wells at different potential9[SUBM 18]1.3Minimum spacing between wells at same potential0 or 61.4Minimum spacing between wells of different type(if both are drawn)0Table 6: SCMOS Layout Rules – WellSCMOS Layout Rules – Active

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   RuleDescriptionLambda2.1Minimum width32.2Minimum spacing32.3Source/drain active to well edge5[SUBM 6]2.4Substrate/well contact active to well edge32.5Minimum spacing between active of different implant0 or 4Table 7: SCMOS Layout Rules – ActiveSCMOS Layout Rules – PolyRuleDescriptionLambda3.1Minimum width23.2Minimum spacing2[SUBM 3]3.3Minimum gate extension of active23.4Minimum active extension of poly33.5Minimum field poly to active1Table 8: SCMOS Layout Rules – Poly

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   SCMOS Layout Rules – SelectRuleDescriptionLambda4.1Minimum select spacing to channel of transistorto ensure adequate source/drain width34.2Minimum select overlap of active24.3Minimum select overlap of contact14.4Minimum select width and spacing(Note: P-select and N-select may be coincident,but mustnotoverlap) (not illustrated)2Table 9: SCMOS Layout Rules – Select

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   SCMOS Layout Rules – Simple Contact to PolyOn HP’s CMOS14 process (and probably on all subsequent processes as they evolve), HP requiresthat ALL features on the insulator layers (CONTACT, VIA, VIA2) MUST BE of the singlestandard size; there are no exceptions for pads (or logos, or anything else); large openings must bereplaced by an array of standard sized openings.RuleDescriptionLambda5.1Exact contact size2 x 25.2Minimum poly overlap1.55.3Minimum contact spacing2[SUBM 3]5.4Minimum spacing to gate of transistor2Table 10: SCMOS Layout Rules – Simple Contact to Poly

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    SCMOS Layout Rules – Simple Contact to ActiveRuleDescriptionLambda6.1Exact contact size2 x 26.2Minimum active overlap1.56.3Minimum contact spacing2[SUBM 3]6.4Minimum spacing to gate of transistor2Table 11: SCMOS Layout Rules – Simple Contact to Active

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    SCMOS Layout Rules – Alternative Contact to PolyThe rules above are preferred. If, however, one cannot handle the 1.5 lambda contact overlap in5.2, then that rule, 5.2, may be replaced by these rules, which reduce the overlap, but increase thespacing to surrounding features. The remaining rules above, 5.1, 5.3, and 5.4, still apply asoriginally stated.RuleDescriptionLambda5.2.bMinimum poly overlap15.5.bMinimum spacing to other poly4[SUBM 5]5.6.bMinimum spacing to active (one contact)25.7.bMinimum spacing to active (many contacts)3Table 12: SCMOS Layout Rules – Alternative Contact to PolySCMOS Layout Rules – Alternative Contact to ActiveThe rules above are preferred. If, however, one cannot handle the 1.5 lambda contact overlap in6.2, then that rule, 6.2, may be replaced by these rules, which reduce the overlap, but increase thespacing to surrounding features. The remaining rules above, 6.1, 6.3, and 6.4, still apply asoriginally stated.

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    RuleDescriptionLambda6.2.bMinimum active overlap16.5.bMinimum spacing to diffusion active56.6.bMinimum spacing to field poly (one contact)26.7.bMinimum spacing to field poly (many contacts)36.8.bMinimum spacing to poly contact4Table 13: SCMOS Layout Rules – Alternative Contact to ActiveSCMOS Layout Rules – Metal1RuleDescriptionLambda7.1Minimum width37.2.aMinimum spacing37.2.bMinimum tight metal spacing(only allowed between minimum width wires -otherwise, use regular spacing rule)27.3Minimum overlap of any contact1Table 14: SCMOS Layout Rules – Metal1

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    SCMOS Layout Rules – Via1RuleDescriptionLambda8.1Exact size2 x 28.2Minimum via1 spacing38.3Minimum overlap by metal118.4Minimum spacing to contact28.5Minimum spacing to poly or active edge2Table 15: SCMOS Layout Rules – Via1

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    SCMOS Layout Rules – Metal2RuleDescriptionLambda9.1Minimum width39.2.aMinimum spacing49.2.bMinimum tight metal or SUBM spacing(only allowed between minimum width wires -otherwise, use regular spacing rule)39.3Minimum overlap of via11Table 16: SCMOS Layout Rules – Metal2SCMOS Layout Rules – OverglassNote that rules in this section are in units of microns.They are not “true” design rules, but they do make goodpractice rules. Unfortunately, there are no really good genericpad design rules since pads are process-specific.

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    RuleDescriptionMicrons10.1Minimum bonding pad width100 x 10010.2Minimum probe pad width75 x 7510.3Pad metal overlap of glass opening610.4Minimum pad spacing to unrelated metal2(and metal3 if triple metal is used)3010.5Minimum pad spacing to unrelated metal1,poly, electrode or active15Table 17: SCMOS Layout Rules – OverglassSCMOS Layout Rules – Electrode for Capacitor (Analog Option)The new layer in this option is the electrode layer, which is a second polysilicon layer (physicallyabove the standard, or first, poly layer). The oxide between the two polys is the capacitordielectric. The capacitor area is the area of coincident poly and electrode.

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    RuleDescriptionLambda11.1Minimum width311.2Minimum spacing311.3Minimum poly overlap211.4Minimum spacing to active or well edge(not illustrated)211.5Minimum spacing to poly contact3Table 18: SCMOS Layout Rules – Electrode for Capacitor (Analog Option)SCMOS Layout Rules – Electrode for Transistor (Analog Option)Same electrode (second poly) layer as above.RuleDescriptionLambda12.1Minimum width212.2Minimum spacing312.3Minimum electrode gate overlap of active212.4Minimum spacing to active112.5Minimum spacing or overlap of poly212.6Minimum spacing to poly or active contact3Table 19: SCMOS Layout Rules – Electrode for Transistor (Analog Option)

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    SCMOS Layout Rules – Electrode Contact (Analog Option)The electrode is contacted through the standard contact layer, similar to the first poly. Theoverlap numbers are larger, however.RuleDescriptionLambda13.1Exact contact size2 x 213.2Minimum contact spacing213.3Minimum electrode overlap (on capacitor)313.4Minimum electrode overlap (not on capacitor)213.5Minimum spacing to poly or active3Table 20: SCMOS Layout Rules – Electrode Contact (Analog Option)

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    SCMOS Layout Rules – Via2 (Triple Metal Option)RuleDescriptionLambda14.1Exact size2 x 214.2Minimum spacing314.3Minimum overlap by metal2114.4Minimum spacing to via1214.5Via2 may be placed over contactTable 21: SCMOS Layout Rules – Via2 (Triple Metal Option)

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    SCMOS Layout Rules – Metal3 (Triple Metal Option)RuleDescriptionLambda15.1Minimum width6[SUBM 5]15.2Minimum spacing to metal34[SUBM 3]15.3Minimum overlap of via22Table 22: SCMOS Layout Rules – Metal3 (Triple Metal Option)

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    SCMOS Layout Rules – NPN Bipolar Transistor (Analog Option)The new layer in this option is the pbase layer, which is an active area that is implanted with thepbase implant to form the base. The base contact is enclosed in p-select. The emitter is an n-selectregion within (and on top of) the base. The entire pbase sits in an n-well that is the collector. Thecollector contact is a well contact, but the overlaps are larger.

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    RuleDescriptionLambda16.1All active contact2 x 216.2Minimum emitter select overlap of contact316.3Minimum pbase overlap of emitter select216.4Minimum spacing between emitter selectand base select416.5Minimum pbase overlap of base select216.6Minimum base select overlap of contact216.7Minimum nwell overlap of pbase616.8Minimum spacing between pbase and collector active416.9Minimum collector active overlap of contact216.10Minimum nwell overlap of collector active316.11Minimum select overlap of collector active2Table 23: SCMOS Layout Rules – NPN Bipolar Transistor (Analog Option)

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    SCMOS Layout Rules – Capacitor Well (Linear Capacitor Option)This illustration applies only to CMOS34. Note that the smaller values apply only to CMOS34; thelarger values apply to CMOS14.

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    RuleDescriptionLambda17.1Minimum width10[SUBM 12]17.2Minimum spacing9[SUBM 18]17.3Minimum spacing to external active5[SUBM 6]17.4Minimum overlap of active(This rule was 3 lambda for CMOS34process use, and that smaller value is stillacceptable for layout intended for thatprocess only.)5[SUBM 6]Table 24: SCMOS Layout Rules – Capacitor Well (Linear Capacitor Option)SCMOS Layout Rules – Linear Capacitor (Linear Capacitor Option)This illustration applies only to CMOS34. Note that the smaller values apply only to CMOS34; thelarger values apply to CMOS14.RuleDescriptionLambda18.1Minimum width318.2Minimum poly extension of active1/218.3Minimum active overlap of poly318.4Minimum poly contact to active218.5Minimum active contact to poly4/6

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    Table 25: SCMOS Layout Rules – Linear Capacitor (Linear Capacitor Option)SCMOS Layout Rules – Buried Channel CCD (2um Analog Option)RuleDescriptionLambda19.1Minimum CCD channel active width419.2Minimum CCD channel active spacing419.3Minimum CCD implant overlap of channel active219.4Minimum outside contact to CCD implant319.5Minimum select overlap of electrode (or poly)219.6Minimum poly/electrode overlap within channel active219.7Minimum contact to channel electrode (or poly)2Table 26: SCMOS Layout Rules – Buried Channel CCD (2um Analog Option)

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    SCMOS Layout Rules – Silicide BlockRuleDescriptionLambda20.1Minimum SB width420.2Minimum SB spacing420.3Minimum spacing, SB to contact(no contacts allowed inside SB)220.4Minimum spacing, SB to external active220.5Minimum spacing, SB to external poly220.6Resistor is poly inside SB; poly ends stick outfor contacts must be outside well and over field20.7Minimum poly width in resistor520.8Minimum spacing of poly resistors(in a single SB region)720.9Minimum SB overlap of poly2Table 27: SCMOS Layout Rules – Silicide Block

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    SCMOS Layout Rules – Via3 (Quad Metal option)A fourth metal layer will be available around the time of the 0.5 um feature size regime. Inprocesses with four metal layers, the third metal is made thinner and therefore has the samelayout rules as the second metal. Rules 15.1 and 15.3 are therefore revised in this option. Theserules are designed for the SUBM variant directly.RuleDescriptionLambda15.1Minimum Metal3 width3(not illustrated)15.3Minimum Metal3 overlap of VIA21(not illustrated)21.1Exact size2 x 221.2Minimum spacing421.3Minimum overlap by Metal31

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    Table 28: SCMOS Layout Rules – Via3 (Quad Metal Option)SCMOS Layout Rules – Metal4 (Quad Metal Option; SUBM only)RuleDescriptionLambda22.1Minimum width622.2Minimum spacing to Metal4622.3Minimum overlap of Via32

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    Table 29: SCMOS Layout Rules – Metal4 (Quad Metal option)SCMOS Layout Rules – SCNPC with POLY_CAP1The two plates of an SCNPC capacitor are POLY and POLY_CAP1. The POLY_CAP1 mustsurround the POLY everywhere; the area of the capacitor is the area of the POLY. POLY isphysically on top of POLY_CAP1, so that contact to the POLY_CAP1 must be made in the regionwhere it extends beyond the POLY. The capacitor may be in the well or the substrate, but may notstraddle a well boundary. The only metal that may cross over a capacitor is the connectingMETAL1 wires.

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    RuleDescriptionLambda23.1Minimum POLY_CAP1 widthThis is lithographic; the minimumto build a real capacitor isgreater than 12 lambda823.2Minimum spacing, POLY_CAP1 to POLY_CAP1(neighboring capacitor)423.3Minimum spacing, POLY_CAP1 to ACTIVE(all capacitors must be over field)823.4Minimum overlap, POLY_CAP1 over POLY323.5Minimum overlap, POLY_CAP1 over CONTACT223.6Minimum overlap, POLY over CONTACT(in a capacitor only; still 1 lambda elsewhere)223.7Minimum spacing, POLY to CONTACT-to-POLY_CAP1223.8Minimum spacing, unrelated METAL1 to POLY_CAP1423.9Minimum spacing, METAL2 to POLY_CAP12

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    Table 30: SCMOS Layout Rules – SCNPC with POLY_CAP1

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